A methodology and framework to assist in the architecture design and functional verification of complex electronic systems.
An integrated, powerful and flexible development environment has been created in this research work in order to simulate and verify electronic systems starting from a very high abstraction level. The system architecture design, the algorithm tuning and the functional verification can be performed...
| Main Authors: | , , |
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| Format: | info:eu-repo/semantics/doctoralThesis |
| Language: | eng |
| Published: |
2013
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10171/34245 |
| _version_ | 1793400565044084736 |
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| author | Tomasena-Arriaga, K. (Koldo) Velez-Isasmendi, I. (Igone) Sevillano Berasategui, J. F. (Juan Francisco) |
| author_facet | Tomasena-Arriaga, K. (Koldo) Velez-Isasmendi, I. (Igone) Sevillano Berasategui, J. F. (Juan Francisco) |
| author_sort | Tomasena-Arriaga, K. (Koldo) |
| collection | DSpace |
| description | An integrated, powerful and flexible development environment has been
created in this research work in order to simulate and verify electronic systems
starting from a very high abstraction level. The system architecture
design, the algorithm tuning and the functional verification can be performed
efficiently early in the development process by means the proposed
contributions. |
| format | info:eu-repo/semantics/doctoralThesis |
| id | oai:dadun.unav.edu:10171-34245 |
| institution | Universidad de Navarra |
| language | eng |
| publishDate | 2013 |
| record_format | dspace |
| spelling | oai:dadun.unav.edu:10171-342452024-01-09T08:24:59Z A methodology and framework to assist in the architecture design and functional verification of complex electronic systems. Tomasena-Arriaga, K. (Koldo) Velez-Isasmendi, I. (Igone) Sevillano Berasategui, J. F. (Juan Francisco) Transaction Level Modeling (TLM). Assertion-based Verification (ABV). Model-driven Design (MDD). Automatic code generation. SystemC. An integrated, powerful and flexible development environment has been created in this research work in order to simulate and verify electronic systems starting from a very high abstraction level. The system architecture design, the algorithm tuning and the functional verification can be performed efficiently early in the development process by means the proposed contributions. 2013-10-22T07:44:46Z 2013-10-22T07:44:46Z 2013-10-22 2013-07-12 info:eu-repo/semantics/doctoralThesis https://hdl.handle.net/10171/34245 eng application/pdf |
| spellingShingle | Transaction Level Modeling (TLM). Assertion-based Verification (ABV). Model-driven Design (MDD). Automatic code generation. SystemC. Tomasena-Arriaga, K. (Koldo) Velez-Isasmendi, I. (Igone) Sevillano Berasategui, J. F. (Juan Francisco) A methodology and framework to assist in the architecture design and functional verification of complex electronic systems. |
| title | A methodology and framework to assist in the architecture design and functional verification of complex electronic systems. |
| title_full | A methodology and framework to assist in the architecture design and functional verification of complex electronic systems. |
| title_fullStr | A methodology and framework to assist in the architecture design and functional verification of complex electronic systems. |
| title_full_unstemmed | A methodology and framework to assist in the architecture design and functional verification of complex electronic systems. |
| title_short | A methodology and framework to assist in the architecture design and functional verification of complex electronic systems. |
| title_sort | methodology and framework to assist in the architecture design and functional verification of complex electronic systems. |
| topic | Transaction Level Modeling (TLM). Assertion-based Verification (ABV). Model-driven Design (MDD). Automatic code generation. SystemC. |
| url | https://hdl.handle.net/10171/34245 |
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